Cypress Semiconductor /psoc63 /I2S0 /RX_CTL

Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. When set to ‘1’, the serial data will be captured 0.5 SCK cycles later than when set to ‘0’.

1. RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge
2. RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1)
3. RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge
4. RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3)

(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. Note: When Slave mode, must be ‘0’. (Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV)

0 (RISING_EDGE_RX): SDI received at SCK rising edge when RX_CTL.SCKO_POL=0

1 (FALLING_EDGE_RX): SDI received at SCK falling edge when RX_CTL.SCKO_POL=0

Specifies number of channels per frame:

Note: only ‘2channels’ is supported during Left Justfied or I2S mode. Hence software must set ‘1’ to this field in the modes. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET)

0 (CH_NUM1): 1 channel

1 (CH_NUM2): 2 channels

2 (CH_NUM3): 3 channels

3 (CH_NUM4): 4 channels

4 (CH_NUM5): 5 channels

5 (CH_NUM6): 6 channels

6 (CH_NUM7): 7 channels

7 (CH_NUM8): 8 channels

Set interface in master or slave mode:

(Note: This bit is connected to AR38U12.TX_CFG.RX_MS)

0 (SLAVE): Slave

1 (MASTER): Master

Select I2S, left-justified or TDM:

(Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)

0 (LEFT_JUSTIFIED): Left Justified

1 (I2S): I2S mode

2 (TDM_A): TDM mode A, the 1st Channel align to WSO Rising Edge

3 (TDM_B): TDM mode B, the 1st Channel align to WSO Rising edge with1 SCK Delay

Set WS pulse width in TDM mode:

(Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) Note: When not TDM mode, must be ‘1’.

0 (SCK_PERIOD): Pulse width is 1 SCK period

1 (CH_LENGTH): Pulse width is 1 channel length

Set watchdog for ‘rx_ws_in’ ‘0’: Disabled. ‘1’: Enabled.

Channel length in number of bits:

Note:

• When this field is configured to ‘6’ or ‘7’, the length is set to 32-bit (same as ‘5’).
• When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN)

0 (BIT_LEN8): 8-bit

1 (BIT_LEN16): 16-bit

2 (BIT_LEN18): 18-bit

3 (BIT_LEN20): 20-bit

4 (BIT_LEN24): 24-bit

5 (BIT_LEN32): 32-bit

Word length in number of bits:

Note:

• When this field is configured to ‘6’ or ‘7’, the length is set to 32-bit (same as ‘5’).
• Don’t configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.RX_CFG.RX_IWL)

0 (BIT_LEN8): 8-bit

1 (BIT_LEN16): 16-bit

2 (BIT_LEN18): 18-bit

3 (BIT_LEN20): 20-bit

4 (BIT_LEN24): 24-bit

5 (BIT_LEN32): 32-bit

When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. ‘0’: Extended by ‘0’ ‘1’: Extended by sign bit (if MSB word is ‘1’, then it is extended by ‘1’, if MSB is ‘0’ then it is extended by ‘0’)

RX master bit clock polarity. When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details.

RX slave bit clock polarity. When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting. ‘0’: When receiver is in slave mode, serial data is sampled on the rising bit clock edge ‘1’: When receiver is in slave mode, serial data is sampled on the falling bit clock edge